1. Field of the Invention
The present invention relates generally to a method and a system for improving a delay error. More specifically, the invention relates to a method and a system for improving a delay error due to circuit layout of a LSI or a printed circuit board, such as a digital logic circuit or the like.
2. Description of the Related Art
Conventionally, a method and a system for improving a delay error of this kind has been used for improving a delay performance of a path which does not satisfy a delay restriction in a layout of an LSI or a printing circuit board.
As prior art, reference is made to Japanese Unexamined Patent Publication (Kokai) Heisei 6-140514; Sho ISHIOKA, Masami MURAKATA, Masako MUROBUSHI, "Experiments and Evaluation of Timing Updating ECO", 6-85, 6-88 (Paper No. 7K-8), Information Processing Society of Japan, No. 45 (latter-half year of 1992), Paper in National Meeting; "Performance-Oriented Synthesis of Large-Scale" (IEEE Transactions on Computer-Aided Design, Vol. CAD-6, No. 5, September, 1987, for example.
In the conventional system, a method for improving delay performance of the critical path is that a delay value is calculated on the basis of a virtual wiring length (length of not fixed wiring but temporarily determined wiring) or an actual wiring length (wiring fixed the path) after wiring process, a critical path (the path which does not satisfy a demanded value or the path close to the demanded value) is extracted, a circuit cell (hereinafter simply referred to as "cell") presenting on the critical path is replaced with a different cell having the same function and a different delay performance, a logical connection information is modified, and subsequently arrangement and wiring process is re-done.
On the other hand, if the delay performance cannot be satisfied merely by replacing with the cell for too large delay, solution has been taken to go back to architecture design for improving delay performance.
In the conventional method as set forth above, even when the delay performance may be improved merely by replacing the cell, it is possible that the delay performance cannot be improved satisfactorily.
This is because that after changing the cell to that having different delay performance, all of the layout and wiring process is re-done from the beginning, and there is no guarantee that the layout position and wiring length are the same as that before changing the cell.